The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices.
Integrated circuits fabricated in semiconductor on insulator (SOI) technology rely on adjacent field effect transistors (FETs) being electrically isolated from each other. However, when coupled with the need for decreasing the size of the FETs, such as, for example, in very-large-scale integration (VLSI) technologies like high density memory technologies, the very nature of the isolation can create undesired effects in the FETs such as FET to FET leakage and short channel effects.